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| March 2001 Advance Information (R) AS7C256A AS7C3256A 5V/3.3V 32K X 8 CMOS SRAM (Common I/O) Features * AS7C256A (5V version) * AS7C3256A (3.3V version) * Industrial and commercial temperature * Organization: 32,768 words x 8 bits * High speed - 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time * Very low power consumption: STANDBY - 11 mW (AS7C256A) / max CMOS I/O - 3.6 mW (AS7C3256A) / max CMOS I/O * Latest 6T 0.25u CMOS technology * 2.0V data retention * Easy memory expansion with CE and OE inputs * TTL-compatible, three-state I/O * 28-pin JEDEC standard packages * ESD protection 2000 volts * Latch-up current 200 mA - 300 mil SOJ - 8 x 13.4 TSOP * Very low power consumption: ACTIVE - 495mW (AS7C256A) / max @ 10 ns - 216mW (AS7C3256A) / max @ 10 ns Logic block diagram VCC GND Input buffer Pin arrangement 28-pin TSOP I (8x13.4) 28-pin SOJ (300 mil) A0 A1 A2 A3 A4 A5 A6 A14 I/O7 Row decoder Sense amp 256 X 128 X 8 Array (262,144) OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (22) (23) (24) (25) (26) (27) (28) AS7C256A (1) AS7C3256A (2) (3) (4) (5) (6) (7) (21) 28 (20) 27 (19) 26 (18) 25 (17) 24 (16) 23 (15) 22 (14) 21 (13) 20 (12) 19 (11) 18 (10) 17 (9) 16 (8) 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 I/O0 Note: This part is compatible with both pin numbering conventions used by various manufacturers. A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Column decoder WE Control circuit OE CE A 7 A 8 AAAAA 9 10 11 12 13 Selection guide AS7C256A-10 AS7C3256A-10 AS7C256A-12 AS7C3256A-12 AS7C256A-15 AS7C3256A-15 AS7C256A-20 AS7C3256A-20 Unit Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current AS7C256A AS7C3256A AS7C256A AS7C3256A 10 3 90 60 2 1 12 3 80 50 2 1 15 4 70 45 2 1 20 5 70 45 5 2 AS7C256A AS7C3256A ns ns mA mA mA mA 3/7/01; V.0.9.2 Alliance Semiconductor P. 1 of 8 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C256A AS7C3256A (R) Functional description The AS7C(3)256A is a 5V/3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words x 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance's advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins. . The device enters standby mode when CE is high. CMOS standby mode consumes 3.6 mW Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Both versions of the AS7C256A offer 2.0V data retention. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. . A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/ O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW with write enable (WE) high. The chip , drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible and 5V tolerant. Operation is from a single 3.30.3V supply. The AS7C(3)256A is packaged in high volume industry standard packages. Absolute maximum ratings Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Device AS7C256A AS7C3256A Symbol Vt1 Vt1 Vt2 PD Tstg Tbias IOUT Min -0.5 -0.5 -0.5 - -65 -55 - Max +7.0 +5.0 VCC + 0.5 1.0 +150 +125 20 Unit V V V W o o C C mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE H L L L WE X H H L OE X H L X Data High Z High Z DOUT DIN Mode Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC) Key: X = Don't care, L = Low, H = High 3/7/01; V.0.9.2 Alliance Semiconductor P. 2 of 8 (R) AS7C256A AS7C3256A Recommended operating conditions Parameter Supply voltage Device AS7C256A AS7C256A Input voltage -- Ambient operating temperature * VIL min = -2.0V for pulse width less than tRC/2. Symbol VCC VIH VIL TA * Min 4.5 3.0 2.2 2.0 -0.5 0 -40 * Typical 5.0 3.3 - - - - - Max 5.5 3.6 VCC+0.5 VCC+0.5 0.8 70 85 Unit V V V V V oC o AS7C3256A VCC AS7C3256A VIH commercial TA industrial C DC operating characteristics (over the operating range)1 -10 Parameter Input leakage current Sym |ILI| Test conditions VCC = Max, Vin = GND to VCC VCC = Max, VOUT = GND to VCC VCC = Max, CE VIL f = fMax, IOUT = 0mA VCC = Max, CE VIL f = fMax, IOUT = 0mA Device Both Both AS7C256A AS7C3256A AS7C256A AS7C3256A -12 Min - - 90 60 30 30 2 1 - - - - - - - 2.4 Max 1 1 80 50 25 25 2 1 0.4 - -15 Min - - - - - - - - - 2.4 Max 1 1 70 45 20 20 2 1 0.4 - -20 Min - - - - - - - - - 2.4 Max Unit 1 1 70 45 20 20 5.0 2.0 0.4 - mA V V mA A A Min Max Output leakage |ILO| current Operating power supply current ICC ISB Standby power supply current ISB1 VOL VOH mA VCC = Max, CE > VCC-0.2V AS7C256A VIN < GND + 0.2V or AS7C3256A VIN > VCC-0.2V, f = 0 IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min VCC = 2.0V CE > VCC -0.2V Output voltage Both Both Data retention current ICCDR Both .5 .5 .5 1 mA VIN > VCC -0.2V or VIN < 0.2V Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)2 Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE I/O Test conditions Vin = 0V Vin = Vout = 0V Max 5 7 Unit pF pF 3/7/01; V.0.9.2 Alliance Semiconductor P. 3 of 8 AS7C256A AS7C3256A (R) Read cycle (over the operating range)3,9 -10 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change CE LOW to output in low Z CE HIGH to output in high Z OE LOW to output in low Z OE HIGH to output in high Z Power up time Power down time Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tOHZ tPU tPD Min 10 2 0 0 0 Max 10 10 3 3 3 10 12 - - - 3 0 - 0 - 0 - -12 Min Max - 12 12 3 - - 3 - 3 - 12 15 - - - 3 0 - 0 - 0 - -15 Min Max - 15 15 4 - - 4 - 4 - 15 20 - - - 3 0 - 0 - 0 - -20 Min Max - 20 20 5 - - 5 - 5 - 20 Unit ns ns ns ns ns ns ns ns ns ns ns 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 3 3 Notes Key to switching waveforms Rising input Falling input Undefined output/don't care Read waveform 1 (address controlled)3,6,7,9 tRC Address tAA Dout Data valid tOH Read waveform 2 (CE controlled)3,6,8,9 tRC1 CE tOE OE tOLZ tACE Dout tCLZ Supply current tPU 50% Data valid tPD 50% ICC ISB tOHZ tCHZ 3/7/01; V.0.9.2 Alliance Semiconductor P. 4 of 8 (R) AS7C256A AS7C3256A Write cycle (over the operating range)11 -10 Parameter Write cycle time Chip enable to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Shaded areas contain advance information. -12 Min 12 10 9 0 8 0 6 0 - 1 Max - - - - - - - - 6 - -6 15 12 10 0 9 0 8 0 - 1 -15 Min Max - - - - - - - - 6 - 20 12 12 0 12 0 10 0 - 2 -20 Min Max - - - - - - - - 6 - Unit ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 Notes Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Min 10 8 8 0 7 0 5 0 1 Max Write waveform 1 (WE controlled)10,11 tWC tAW Address tWP WE tAS Din tWZ Dout tDW Data valid tOW tDH tAH Write waveform 2 (CE controlled)10,11 tWC tAW Address tAS CE tWP WE tWZ Din Dout tDW Data valid tDH tCW tAH 3/7/01; V.0.9.2 Alliance Semiconductor P. 5 of 8 AS7C256A AS7C3256A (R) Data retention characteristics (over the operating range) Parameter VCC for data retention Operation recovery time Input leakage current Symbol VDR tR | ILI | Test conditions VCC = 2.0V CE VCC -0.2V VIN VCC -0.2V or VIN 0.2V Min 2.0 0 tRC - Max - - - 1 Unit V ns ns A Chip enable to data retention time tCDR Data retention waveform Data retention mode VCC VCC VDR 2.0V VCC tCDR CE VIH VDR VIH tR AC test conditions Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. +5V 480 +3.0V GND 90% 10% 2 ns 90% 10% Dout 255 C(14) Dout 350 Thevenin equivalent 168 Dout +1.72V (5V and 3.3V) +3.3V 320 C(14) Figure A: Input pulse GND Figure B: Output load GND Figure C: Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, C. These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. C=30pF, except on High Z and Low Z parameters, where C=5pF. 3/7/01; V.0.9.2 Alliance Semiconductor P. 6 of 8 (R) AS7C256A AS7C3256A Package diagrams e D B A E1 E2 A1 b 28-pin SOJ Min Max A A1 A2 B b c D E E1 E2 e 0.025 0.095 0.140 0.105 Seating Plane 0.028 TYP 0.018 TYP 0.010 TYP 0.245 0.295 0.327 0.730 0.285 0.305 0.347 Pin 1 A2 E c 0.050 BSC b e c L A2 A A1 28-pin TSOP 8x13.4 Min Max A A1 A2 - 0.10 0.95 0.15 0.10 11.60 1.20 0.20 1.05 0.25 0.20 11.80 D pin 1(22) Hd pin 8(21) pin 1(7) 28-pin E pin 5(8) b c D e E Hd L 0.55 nominal 8.0 nominal 13.30 0.50 0 13.50 0.70 5 Note: This part is compatible with both pin numbering conventions used by various manufacturers. 3/7/01; V.0.9.2 Alliance Semiconductor P. 7 of 8 AS7C256A AS7C3256A (R) Ordering information Package / Access time Volt/Temp 5V commercial Plastic SOJ, 300 mil 3.3V commercial 5V industrial 3.3V industrial 5V commercial TSOP 8x13.4 3.3V commercial 5V industrial 3.3V industrial 10 ns AS7C256A-10JC AS7C3256A-10JC AS7C256A-10JI AS7C3256A-10JI AS7C256A-10TC AS7C3256A-10TC AS7C256A-10TI AS7C3256A-10TI 12 ns AS7C256A-12JC AS7C3256A-12JC AS7C256A-12JI AS7C3256A-12JI AS7C256A-12TC AS7C3256A-12TC AS7C256A-12TI AS7C3256A-12TI 15 ns AS7C256A-15JC AS7C3256A-15JC AS7C256A-15JI AS7C3256A-15JI AS7C256A-15TC AS7C3256A-15TC AS7C256A-15TI AS7C3256A-15TI 20 ns AS7C256A-20JC AS7C3256A-20JC AS7C256A-20JI AS7C3256A-20JI AS7C256A-20TC AS7C3256A-20TC AS7C256A-20TI AS7C3256A-20TI Part numbering system AS7C 3 256A -XX X C or I Commercial temperature range: 0 oC to 70 0C Industrial temperature range: -40C to 85C SRAM prefix 3 = 3.3V supply Device number Access time Package: J T = SOJ 300 mil = TSOP 8x13.4 3/7/01; V.0.9.2 Alliance Semiconductor P. 8 of 8 (c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. |
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